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IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT LATCHED TRANSCEIVER
FEATURES:
* * * * * * * *
IDT74FCT162543AT/CT
0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) VCC = 5V 10% Balanced Output Drivers: 24mA Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V, TA = 25C * Available in SSOP and TSSOP packages
The FCT162543T 16-bit latched transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be low in order to enter data from the A port or to output data from the B port. xLEAB controls the latch function. When xLEAB is low, the latches are transparent. A subsequent low-to-high transition of xLEAB signal puts the A latches in the storage mode. xOEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using xCEBA, xLEBA, and xOEBA inputs. Flowthrough organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT162543T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. The FCT162543T is a plug-in replacement for the FCT16543T and 54/74ABT16543 for on-board bus interface applications.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
1OEBA
56
2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB
29 31 30 28 26 27
1CEBA 54 1LEBA 1OEAB 1CEAB 1LEAB
55 1 3 2
C
1A1 5
2A1 15
52
C D C D
42
D C D
1B1
2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-5445/3
IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OEAB 1LEAB 1CEAB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA
56 55 54 53 52 51 50 49
1OEBA 1LEBA 1CEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(2) VTERM(3) TSTG IOUT
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
NOTE: 1. This parameter is measured at characterization but not tested.
VCC
2A7 2A8
VCC
2B7 2B8
GND
2CEAB 2LEAB 2OEAB
GND
2CEBA 2LEBA 2OEBA
FUNCTION TABLE(1, 2)
For A-to-B (Symmetric with B-to-A)
Inputs xLEAB X H L H L H Latch Status xAx to xBx Storing Storing Transparent Storing Transparent Storing Output Buffers xBx Z X Current A Inputs Previous* A Inputs Z Z
SSOP/ TSSOP TOP VIEW xCEAB H X L L L L
PIN DESCRIPTION
Pin Names xOEAB xOEBA xCEAB xCEBA xLEAB xLEBA xAx xBx Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
xOEAB X X L L H H
NOTES: 1. * Before xLEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedence 2. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA and xOEBA.
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IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins)(5) Input HIGH Current (I/O pins)(5) IIL Input LOW Current (Input pins)(5) Input LOW Current (I/O pins)(5) IOZH IOZL VIK IOS VH ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins)(5) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VO = VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL 1.5V(3) VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) IOH = -24mA IOH = 24mA Min. 60 -60 2.4 -- Typ.(2) 115 -115 3.3 0.3 Max. 200 -200 -- 0.55 Unit mA mA V V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is 5A at TA = -55C.
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IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open xCEAB and xOEAB = GND xCEBA = VCC One Input Togging 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB = GND xCEBA = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle xLEAB, xCEBA and xOEAB = GND xCEBA = VCC Sixteen Bit Toggling VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 60 Max. 1.5 100 Unit mA A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.6
1.5
mA
VIN = 3.4V VIN = GND VIN = VCC VIN = GND
--
0.9
2.3
--
2.4
4.5(5)
VIN = 3.4V VIN = GND
--
6.4
16.5(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay Transparent Mode xAx to xBx or xBx to xAx Propagation Delay xLEBA to xAx, xLEAB to xBx Output Enable Time xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx Output Disable Time xOEBA or xOEAB to xAx or xBx xCEBA or xCEAB to xAx or xBx Set-up Time HIGH or LOW xAx or xBx to xLEAB or xLEBA Hold Time HIGH or LOW xAx or xBx to xLEAB or xLEBA xLEBA or xLEAB Pulse Width LOW Output Skew(3) Condition(1) CL = 50pF RL = 500 74FCT162543AT Min.(2) Max. 1.5 6.5 74FCT162543CT Min.(2) Max. 1.5 3.5 Unit ns
1.5 1.5
8 9
1.5 1.5
4.1 4.8
ns ns
1.5
7.5
1.5
4
ns
2 2 4 --
-- -- -- 0.5
1 1 3(4) --
-- -- -- 0.5
ns ns ns ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.
5
IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
tSU
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ DISABLE 3V 1.5V 0V 3.5V 0.3V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT162543AT/CT FAST CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT Temp. Range XXX Family XXXX Device Type XX Package
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
543AT 543CT
16-Bit Latched Transceiver
162
Double-Density, 5 Volt, Balanced Drive
74
- 40C to +85C
DATA SHEET DOCUMENT HISTORY 3/28/2002 5/21/2002 6/20/2002 Removed standard speed grade Removed TVSOP package Updated as per PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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